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LM10507 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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LM10507 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 40 page LM10507 SNVS999 – MAY 2014 www.ti.com Pin Functions (continued) Pin I/O Description Name No. SPI_CLK C1 I SPI Interface – serial clock input Digital Input Control Signal to Enable/Disable PMIC. Signal Level is related to VIN_IO. This ENABLE G4 I is an active High pin with an internal pull-down resistor. GND F4 I Digital Input Control Signal – Not Used – Connect to GND. Digital Input Control Signal for entering Device Sleep Mode – see table 1. This is an active DEVSLP E7 I High pin with an internal pull-down resistor. Digital Input Control Signal to abort SPI transactions and resets the PMIC to default RESET F7 I Voltages. This is an active Low pin with an internal pull-up resistor. GND C7 I Not Used – Connect to GND. PWR_OK A1 O Digital Output of Power Good signal – all output rails are started. Supply Voltage for Digital Interface Signals to ASIC like SPI, RESET, DEVSLP, ENABLE, VIN_IO B1 P PWR_OK. GND B2 G Ground. Connect to system Ground. GND B3 G Ground. Connect to system Ground. GND D7 G Ground. Connect to system Ground. A: Analog Pin D : Digital Pin G: Ground Pin P: Power Pin I: Input Pin O: Output Pin 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LM10507 |
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