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AD5641AKS Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD5641AKS Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 20 page AD5641 Preliminary Technical Data Rev. PrC | Page 4 of 20 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2. Table 3. Parameter Limit1 Unit Test Conditions/Comments t12 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 12 ns min SCLK low time t4 13 ns min SYNC to SCLK falling edge setup time t5 5 ns min Data setup time t6 4.5 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t8 33 ns min Minimum SYNC high time t9 13 ns min SYNC rising edge to next SCLK fall ignore 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 30 MHz. t4 t3 t2 t5 t7 t6 D0 D1 D2 D14 D15 DIN SYNC SCLK t9 t1 t8 D15 D14 Figure 2. Timing Diagram |
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