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74ALVCH16646DLG4 Scheda tecnica(PDF) 8 Page - Texas Instruments |
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74ALVCH16646DLG4 Scheda tecnica(HTML) 8 Page - Texas Instruments |
8 / 18 page www.ti.com TIMING REQUIREMENTS SWITCHING CHARACTERISTICS OPERATING CHARACTERISTICS SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032F – JULY 1995 – REVISED SEPTEMBER 2004 over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 4) VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.7 V ± 0.2 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency (1) 150 150 150 MHz tw Pulse duration CLKAB or CLKBA high or low (1) 3.3 3.3 3.3 ns tsu Setup time A before CLKAB ↑ or B before CLKBA↑ (1) 1.6 1.7 1.4 ns th Hold time A after CLKAB ↑ or B after CLKBA↑ (1) 0.6 0.4 0.7 ns (1) This information was not available at the time of publication. over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 4) VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.7 V FROM TO ± 0.2 V ± 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MIN MAX MIN MAX MIN MAX fmax (1) 150 150 150 MHz A or B B or A (1) 1 4.8 4.5 1 3.9 tpd CLKAB or CLKBA (1) 1 5.6 5.2 1 4.5 ns A or B SAB or SBA (1) 1 6.8 6.4 1 5.3 ten OE A or B (1) 1 6.5 6.2 1 5.1 ns tdis OE A or B (1) 1.6 5.7 5 1.4 4.7 ns ten DIR A or B (1) 1 7.8 6.2 1 5.1 ns tdis DIR A or B (1) 1.5 6.5 6 1.1 5.3 ns (1) This information was not available at the time of publication. T A = 25°C VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V PARAMETER TEST CONDITIONS UNIT TYP TYP TYP Outputs enabled (1) 39 43 Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz pF Outputs disabled (1) 10 12 (1) This information was not available at the time of publication. 8 |
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