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ADCS7476 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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ADCS7476 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 33 page 9 ADCS7476, ADCS7477, ADCS7478 www.ti.com SNAS192G – APRIL 2003 – REVISED MAY 2016 Product Folder Links: ADCS7476 ADCS7477 ADCS7478 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated Electrical Characteristics – ADCS7478 (continued) TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Power consumption, normal mode (operational) VDD = 5 V, fSAMPLE = 1 MSPS TA = 25°C 10 mW –40°C ≤ TA ≤ 85°C 17.5 VDD = 3 V, fSAMPLE = 1 MSPS TA = 25°C 2 mW –40°C ≤ TA ≤ 85°C 4.8 Power consumption, shutdown mode VDD = 5 V, SCLK Off 2.5 µW VDD = 3 V, SCLK Off 1.5 ANALOG INPUT CHARACTERISTICS VIN Input range 0 to VDD V IDCL DC leakage current –40°C ≤ TA ≤ 85°C ±1 µA CINA Analog input capacitance 30 pF DIGITAL INPUT CHARACTERISTICS VIH Input high voltage –40°C ≤ TA ≤ 85°C 2.4 V VIL Input low voltage VDD = 5 V, –40°C ≤ TA ≤ 85°C 0.8 V VDD = 3 V, –40°C ≤ TA ≤ 85°C 0.4 V IIN Digital input current VIN = 0 V or VDD TA = 25°C ±10 nA –40°C ≤ TA ≤ 85°C ±1 µA CIND Input capacitance TA = 25°C 2 p –40°C ≤ TA ≤ 85°C 4 DIGITAL OUTPUT CHARACTERISTICS VOH Output high voltage ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C VDD − 0.2 V VOL Output low voltage ISINK = 200 µA, –40°C ≤ TA ≤ 85°C 0.4 V IOL TRI-STATE leakage current –40°C ≤ TA ≤ 85°C ±10 µA COUT TRI-STATE output capacitance 2 4 pF Output coding Straight (natural) binary AC ELECTRICAL CHARACTERISTICS fSCLK Clock frequency –40°C ≤ TA ≤ 85°C 20 MHz DC SCLK duty cycle –40°C ≤ TA ≤ 85°C 40% 60% tTH Track or hold acquisition time –40°C ≤ TA ≤ 85°C 400 ns fRATE Throughput rate –40°C ≤ TA ≤ 85°C (see Application Information) 1 MSPS tAD Aperture delay 3 ns tAJ Aperture jitter 30 ps (1) All input signals are specified as tr = tf = 5 ns (10% to 90% VDD) and timed from 1.6 V. (2) Minimum quiet time required between bus relinquish and start of next conversion. (3) Measured with the load circuit (Figure 1), and defined as the time taken by the output to cross 1 V. 6.8 Timing Requirements –40°C ≤ TA ≤ 85°C, VDD = 2.7 V to 5.25 V, and fSCLK = 20 MHz (unless otherwise noted) (1) PARAMETER CONDITIONS MIN TYP MAX UNIT tCONVERT TA = 25°C 16 × tSCLK tQUIET Quiet time(2) 50 ns t1 Minimum CS pulse width 10 ns t2 CS to SCLK setup time 10 ns t3 Delay from CS until SDATA TRI-STATE disabled (3) 20 ns |
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