CS1112YDWF24 datasheet(6/12 Pages) ONSEMI

Il numero della parte	CS1112YDWF24

Spiegazioni elettronici	Quad Power Output Driver

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SERIAL PERIPHERAL INTERFACE TIMING REQUIREMENTS

CSB (Setup)

CSB

SCLK

SI

SO

SO(Delay)

SO(Rise,Fall)

MSB

SI (Setup)

CSB (Hold)

Xfer Delay

SI (Hold)

70% VDD

30% VDD

Figure 1.

CSB

OUTX

tphl

tplh

tf

tr

Figure 2.

12

3

BLOCK DIAGRAM

+

–

+

–

Gate

Drive

Data 0

Shorted Load

VDD

RESET

IN0 IN1 IN2 IN3

VDD

VPWR

CSB

SI

SCLK

GND

OUT0

OUT1

OUT2

OUT3

10

µA

STATUS

4.0 ms

Fault Timer

Bias

Power On

Reset

Serial D/O

Line Driver

10

µA

10

µA

RESET

Serial

Peripheral

Interface

Overvoltage/

Undervoltage

Lockout

VREG

ILIMIT

RS

1/2 VDD

Data 0

Open Load

Fault 0

Data 0

Data 1 to 3

Fault 1 to 3

OUT

ENABLE

SO

ROSC

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