A0

SEL1

Control Logic

SEL2

A1

A2

A3

A4

A5

A6

A7

B0

B1

B2

B3

B4

B5

B6

B7

C0

C1

C2

C3

C4

C5

C6

C7

EN

B8

B9

B10

B11

C8

C9

C10

C11

A8

A9

A10

A11

TS3DDR4000

www.ti.com

SCDS356A – NOVEMBER 2014 – REVISED MARCH 2015

9 Detailed Description

9.1 Overview

The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The

A port can be routed to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and

DDR4 memory bus systems that support POD_12, SSTL_12, SSTL_135, SSTL_15, or SSTL_18 signaling, the

TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (differential -3dB bandwidth of up to

6.0 GHz), and very low propagation delay and skew across all channels. The TS3DDR4000 is 1.8 V logic

compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a low-

power mode, in which all channels become high-Z and the device operates with minimal power.

9.2 Functional Block Diagram

The following diagram (Figure 18) represents the switch function block diagram of the TS3DDR4000. Port A (A0-

A11) can be routed to either port B (B0-B11) or port C (C0-C11) by configuring the SEL1 and SEL2 pins. The EN

pin can be toggled high to put the device into the low-power mode with minimal power consumption.

Figure 18. TS3DDR4000 Switch Function Block Diagram

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