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LMZ22010 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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LMZ22010 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 36 page LMZ22010 SNVS687H – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT VIN to PGND –0.3 24 V EN, SYNC to AGND –0.3 5.5 V SS, FB, SH to AGND –0.3 2.5 V AGND to PGND –0.3 0.3 V Junction Temperature 150 °C Peak Reflow Case Temperature (30 sec) 245 °C Storage Temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) For soldering specifications, refer to the following document: SNOA549 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) The human body model is a 100-pF capacitor discharged through a 1.5-k Ω resistor into each pin. Test method is per JESD-22-114. 6.3 Recommended Operating Conditions MIN MAX UNIT VIN 6 20 V EN, SYNC 0 5 V Operation Junction Temperature −40 125 °C 6.4 Thermal Information LMZ22010 THERMAL METRIC(1) NDY UNIT 11 PINS Natural Convection 9.9 Junction-to-ambient thermal RθJA 225 LFPM 6.8 °C/W resistance(2) 500 LFPM 5.2 RθJC(top) Junction-to-case (top) thermal resistance 1.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Theta JA measured on a 3.0-in x 3.5-in 4-layer board, with 2-oz. copper on outer layers and 1-oz. copper on inner layers, two hundred and ten thermal vias, and 2-W power dissipation. Refer to evaluation board application note layout diagrams. 4 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22010 |
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