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UC1707-SP Scheda tecnica(PDF) 10 Page - Texas Instruments |
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UC1707-SP Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 20 page 10 UC1707-SP SLUSAG0A – MARCH 2011 – REVISED MARCH 2016 www.ti.com Product Folder Links: UC1707-SP Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Feature Description (continued) (1) If the output was previously in Shutdown and Latch Disable was low and stays low, then even if the Analog Stop Logic is changed or the Shutdown pin is open, the outputs will remain in Shutdown. • Shutdown Pin — This pin serves two purposes. 1. It can be used as an output of the Analog Stop circuit. 2. It can be used as an input to force a shutdown or to force the device out of shutdown. This pin can override both the Analog Stop circuit as well as the Latch Disable Pin. When driving hard logic levels into the Shutdown pin, the Latch Disable functionality will be overridden and the Latch Disable will not function as it does when used in conjunction with the Analog Stop circuit. When the Shutdown pin is high, the outputs will be in the low state (shutdown). When the Shutdown pin is low (hard logic low) the outputs will operate normally, regardless of the state of the Latch Disable pin or the Analog Stop pins. To use the Shutdown Pin with the Latch Disable functional it is necessary to use either a diode in series with the Shutdown signal or to use an open collector pullup so that the Shutdown pin is not pulled low. This configuration will allow the Latch Disable function to work with the Shutdown pin. 8.4 Device Functional Modes Table 1. UG1707 Shutdown Truth Table ANALOG STOP LOGIC SHUTDOWN LATCH DISABLE PREVIOUS STATE OF OUTPUT OUTPUT X 0 X X Follows Input Logic X 1 X X Low (Shutdown) 1 Open X X Low (Shutdown) 0 Open 0 Shutdown Latched Shutdown(1) 0 Open 0 Normal Follows Input Logic 0 Open 1 X Follows Input Logic |
Codice articolo simile - UC1707-SP_16 |
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Descrizione simile - UC1707-SP_16 |
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