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BF1101R Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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BF1101R Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 1999 May 14 7 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. VDS =5 V; Tj =25 C. RG1 =120 k (connected to VGG); see Fig.21. handbook, halfpage 0 40 20 30 10 0 MGS307 26 4 IG1 ( μA) VG2-S (V) 4.5 V 4 V 3.5 V 3 V VGG = 5 V Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. handbook, halfpage 0 0 −30 −20 −10 −40 −50 1 MGS308 234 gain reduction (dB) VAGC (V) (2) (1) (3) VDS =5 V; VGG = 5 V; f = 50 MHz; Tamb =25 C. (1) RG1 =68 k. (2) RG1 =120 k.(3) RG1 = 180 k. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21. handbook, halfpage 0 120 90 100 110 80 10 MGS309 20 30 40 50 Vunw (dB μV) gain reduction (dB) (2) (3) (1) VDS =5 V; VGG = 5 V; f = 50 MHz; funw =60MHz; Tamb =25 C. (1) RG1 =68 k. (2) RG1 =120 k.(3) RG1 = 180 k. Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. handbook, halfpage 0 25 10 15 20 5 0 10 MGS310 20 30 40 50 ID (mA) gain reduction (dB) (2) (3) (1) VDS =5 V; VGG = 5 V; f = 50 MHz; Tamb =25 C. (1) RG1 =68 k. (2) RG1 =120 k.(3) RG1 = 180 k. |
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