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SN74TVC3306 Scheda tecnica(PDF) 8 Page - Texas Instruments |
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SN74TVC3306 Scheda tecnica(HTML) 8 Page - Texas Instruments |
8 / 19 page 150 Ω Open-Drain CPU Interface VREF(1) = 1.5 V GATE(1) B1 (VBIAS)(1) TVC3306 VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to V B3 8 7 6 5 1 2 3 4 150 Ω 200 kΩ B2 VDDREF = 5 V VDPU = 2.5 V A3 A2 A1 BIAS SN74TVC3306 SCDS112D – MARCH 2001 – REVISED DECEMBER 2014 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information Because of the voltage-clamping mechanism, the SN74TVC3306 device performs best as a level translator for signals that have sharp edges (as opposed to analog audio signals). 10.2 Typical Application Figure 3. Typical Application Circuit 8 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: SN74TVC3306 |
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