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SPP07N60S5 Scheda tecnica(PDF) 3 Page - Infineon Technologies AG |
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SPP07N60S5 Scheda tecnica(HTML) 3 Page - Infineon Technologies AG |
3 / 12 page 2004-03-30 Rev. 2.1 Page 3 SPP07N60S5, SPB07N60S5 SPI07N60S5 Electrical Characteristics , at T j = 25 °C, unless otherwise specified Parameter Symbol Conditions Values Unit min. typ. max. Characteristics Transconductance gfs VDS≥2*ID*RDS(on)max, ID=4.6A - 4 - S Input capacitance Ciss VGS=0V, VDS=25V, f =1MHz - 970 - pF Output capacitance Coss - 370 - Reverse transfer capacitance Crss - 10 - Effective output capacitance,3) energy related Co(er) VGS=0V, VDS=0V to 480V - 30 - pF Effective output capacitance,4) time related Co(tr) - 55 - Turn-on delay time td(on) VDD=350V, VGS=0/10V, ID=7.3A, RG=12Ω - 120 - ns Rise time tr - 40 - Turn-off delay time td(off) - 170 255 Fall time tf - 20 30 Gate Charge Characteristics Gate to source charge Qgs VDD=350V, ID=7.3A - 7.5 - nC Gate to drain charge Qgd - 16.5 - Gate charge total Qg VDD=350V, ID=7.3A, VGS=0 to 10V - 27 35 Gate plateau voltage V(plateau) VDD=350V, ID=7.3A - 8 - V 1Repetitve avalanche causes additional power losses that can be calculated asPAV=EAR*f. 2Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. 3Co(er) is a fixed capacitance that gives the same stored energy asCoss while VDS is rising from 0 to 80% VDSS. 4Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. |
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