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SN74AHC273PWG4 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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SN74AHC273PWG4 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 30 page CLK(I) R Q C C D C C C C C C TG C C TG TG TG CLK 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D 5Q 6D 6Q 7D 7Q 8D 8Q CLR 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 11 1 SN54AHC273, SN74AHC273 www.ti.com SCLS376I – JUNE 1997 – REVISED MARCH 2015 9 Detailed Description 9.1 Overview These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The inputs are 5 V tolerant and can be driven from 5-V devices. This feature allows the use of these devices as down translators in a mixed 5-V to 3.3-V system environment. 9.2 Functional Block Diagrams Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN54AHC273 SN74AHC273 |
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