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54ACT175L Scheda tecnica(PDF) 2 Page - National Semiconductor (TI) |
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54ACT175L Scheda tecnica(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Functional Description The ’AC/’ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q out- puts LOW and Q outputs HIGH independent of Clock or Data inputs. The ’AC/’ACT175 is useful for general logic applica- tions where a common Master Reset and Clock are acceptable. Truth Table Inputs Outputs @ t n,MR = H @ t n+1 D n Q n Q n LL H HH L H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Logic Diagram DS100278-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 |
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