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ML4769ES Scheda tecnica(PDF) 8 Page - Micro Linear Corporation |
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ML4769ES Scheda tecnica(HTML) 8 Page - Micro Linear Corporation |
8 / 8 page ML4769 8 © Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 3/26/98 Printed in U.S.A. PHYSICAL DIMENSIONS inches (millimeters) ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML4769CS (Obsolete) 0°C to 70°C 8-Pin SOIC (S08) ML4769ES -20°C to 70°C 8-Pin SOIC (S08) 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com SEATING PLANE 0.148 - 0.158 (3.76 - 4.01) PIN 1 ID 0.228 - 0.244 (5.79 - 6.20) 0.189 - 0.199 (4.80 - 5.06) 0.012 - 0.020 (0.30 - 0.51) 0.050 BSC (1.27 BSC) 0.015 - 0.035 (0.38 - 0.89) 0.059 - 0.069 (1.49 - 1.75) 0.004 - 0.010 (0.10 - 0.26) 0.055 - 0.061 (1.40 - 1.55) 8 0.006 - 0.010 (0.15 - 0.26) 0º - 8º 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) Package: S08 8-Pin SOIC Figure 8. Design Example Schematic Diagram ML4769 VOUT COUT 100µF 10nF CIN 100µF VIN 10µH (Sumida CD54) VL1 VIN GND SENSE PWR GND SHDN VL2 VOUT R2 250k Ω R1 236k Ω SHUTDOWN DS4769-01 |
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