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LM10500 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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LM10500 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 40 page LM10500 SNVS630G – SEPTEMBER 2009 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS Pin # Name Type(1) Function 1,2,27,28 PVIN P Input voltage to the power switches integrated in the device. 3,4,5,6 SW P Switch node output of the power switches. It should be connected to the external inductor. 7,8,9,10 PGND G Power ground for the internal power switches. 11 COMP A Compensation pin to connect to external compensation network. 12 PWROK OD Power Good or PWI Power OK, open drain output. If high, indicates the output voltage is regulated within tolerance. A pull-up resistor (10 k Ω to 100 kΩ) is recommended for most applications. 13 FB A Voltage Feedback pin. This pin can be connected to the output voltage directly or through a resistor divider to set the output voltage range. Range of FB pin voltage is PWI 1.0 or PWI 2.0 programmable between 0.6V and 1.0V. 14 ADDR A PWI Address Selection pin. An external resistor should be connected from this pin to ground to set the PWI 1.0 or PWI 2.0 address. The voltage on this pin is only read once by the internal register when the device is powered up. 15 EN I Precision enable pin. An external divider can be used to set the device turn-on threshold. If not used, the EN pin should be connected to AVIN. 16 FREQ/SYNC A Frequency setting or external clock synchronization pin. This pin can be connected to a resistor to ground to set the internal oscillator frequency. It also can be connected to an external clock source via a capacitor, so that the switching action of the device is synchronized to the external clock. 17 DGND G Digital ground for VPWI and digital interface: SPWI and SCLK. 18 VPWI P PowerWise Interface (PWI) supply input, 1.8 V-10% to 3.3V+10%. A bypass capacitor of 1µF is recommended on this pin. 19 SPWI I/O PowerWise Interface (PWI) bi-directional data pin. This pin is internally pulled down to ground. 20 SCLK I PowerWise Interface (PWI) clock input. This pin is internally pulled down to ground. 21 VDD2 P 2.5V output of internal regulator. This pin is only for bypassing the internal LDO. Loading this pin is not recommended. 22,23 AVIN P Analog power input. It powers the internal 2.5V and 5.0V LDOs, which provide bias current and internal driver power. It can be connected to PVIN through a low pass RC filter, or can be supplied by a separate rail. 24 AGND G Analog ground for the internal bias circuitry. 25 VDD1 P 5.0V output of internal regulator. This pin is only for bypassing the internal LDO. Loading this pin is not recommended. 26 CBOOT A Bootstrap pin to drive the high side switch. A bootstrap capacitor should be connected between this pin to the SW pin. PAD PAD Exposed pad at the back of the device. The PAD should be connected to ground, but cannot be used as primary ground connection. Use multiple vias under the PAD for optimal thermal performance. (1) P: Power, A: Analog, I: Digital Input, I/O: Digital Input/Output, G: Ground, OD: Open Drain These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM10500 |
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