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LM3203 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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LM3203 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 22 page A1 B1 C1 D1 A3 B3 C3 D3 SGND A2 D2 EN BYPOUT PVIN SW PGND VDD FB VCON BYP A3 B3 C3 D3 A1 B1 C1 D1 SGND A2 D2 EN BYPOUT PVIN SW PGND VDD FB VCON BYP LM3203 SNVS355D – MAY 2005 – REVISED APRIL 2013 www.ti.com CONNECTION DIAGRAMS Figure 1. Top View Figure 2. Bottom View 10–Bump Thin DSBGA Package, Large Bump. See NS Package Number YPA0010NHA. PIN DESCRIPTION Pin # Name Description A1 VDD Analog Supply Input. A 0.1 µF ceramic capacitor is recommended to be placed as close to this pin as possible. (Figure 31) B1 VCON Voltage Control Analog input. VCON controls VOUT in PWM mode. (Refer to Setting the Output Voltage) Do not leave floating. C1 FB Feedback Analog Input. Connect to the external resistor divider. (Figure 31) D1 BYP Bypass. Use this digital input to command operation in Bypass mode. Set BYP low for PWM operation. D2 EN Enable Input. Set this digital input high after Vin >2.7V for normal operation. For shutdown, set low. D3 PGND Power Ground C3 SW Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the LM3203. B3 PVIN Power Supply Voltage Input to the internal PFET switch and Bypass FET. (Figure 31) A3 BYPOUT Bypass FET Drain. Connect to the output capacitor. (Figure 31) Connect this pin to VDD when Bypass mode is NOT required. Do not leave floating. A2 SGND Analog and Control Ground These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM3203 |
Codice articolo simile - LM3203_15 |
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Descrizione simile - LM3203_15 |
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