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ISLA110P50IRZ Scheda tecnica(PDF) 4 Page - Intersil Corporation |
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ISLA110P50IRZ Scheda tecnica(HTML) 4 Page - Intersil Corporation |
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4 / 34 page  ISLA110P50 4 FN7606.2 July 25, 2011 Pin Descriptions PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 1, 6, 12, 19, 24, 71 AVDD 1.8V Analog Supply 2, 5, 13, 14, 16, 17, 18, 30, 31, 32, 33, 34, 35 DNC Do Not Connect 3, 4 RES Reserved. (4.7k Ω pull-up to OVDD is required for each of these pins) 7, 8, 11, 72 AVSS Analog Ground 9, 10 VINN, VINP Analog Input Negative, Positive 15 VCM Common Mode Output 20, 21 CLKP, CLKN Clock Input True, Complement 22 OUTMODE Tri-Level Output Mode (LVDS, LVCMOS) 23 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 25 RESETN Power-on Reset (Active Low) 26, 45, 55, 65 OVSS Output Ground 27, 36, 56 OVDD 1.8V Output Supply 28, 29 CLKDIVRSTP, CLKDIVRSTN Sample Clock Synchronous Divider Reset Positive, Negative 37, 38 D0N, D0P [NC, D0] LVDS Bit 0 Output Complement, True [NC, LVCMOS Bit 0] 39, 40 D1N, D1P [NC, D1] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] 41, 42 D2N, D2P [NC, D2] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] 43, 44 D3N, D3P [NC, D3] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] 46 RLVDS LVDS Bias Resistor (connect to OVSS with a 10k Ω, 1% resistor) 47, 48 CLKOUTN, CLKOUTP [NC, CLKOUT] LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] 49, 50 D4N, D4P [NC, D4] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] 51, 52 D5N, D5P [NC, D5] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] 53, 54 D6N, D6P [NC, D6] LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6] 57, 58 D7N, D7P [NC, D7] LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7] 59, 60 D8N, D8P [NC, D8] LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8] 61, 62 D9N, D9P [NC, D9] LVDS Bit 9 (MSB) Output Complement, True [NC, LVCMOS Bit 9] 63, 64 ORN, ORP [NC, OR] LVDS Over-Range Complement, True [NC, LVCMOS Over-Range] 66 SDO SPI Serial Data Output (4.7k Ω pull-up to OVDD is required) 67 CSB SPI Chip Select (active low) 68 SCLK SPI Clock 69 SDIO SPI Serial Data Input/Output 70 OUTFMT Tri-Level Output Data Format (Two’s Comp., Gray Code, Offset Binary) PD AVSS Exposed Paddle. Analog Ground NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection) |
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