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ISL22346UFRT20Z Scheda tecnica(PDF) 2 Page - Intersil Corporation |
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ISL22346UFRT20Z Scheda tecnica(HTML) 2 Page - Intersil Corporation |
2 / 16 page 2 FN6177.2 September 3, 2009 Block Diagram Ordering Information PART NUMBER (Note) PART MARKING RESISTANCE OPTION (k Ω) TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL22346UFV20Z* 22346 UFVZ 50 -40 to +125 20 Ld TSSOP M20.173 ISL22346UFRT20Z* 223 46UFZ 50 -40 to +125 20 Ld 4x4 TQFN L20.4x4A ISL22346WFV20Z* 22346 WFVZ 10 -40 to +125 20 Ld TSSOP M20.173 ISL22346WFRT20Z* 223 46WFZ 10 -40 to +125 20 Ld 4x4 TQFN L20.4x4A *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. I2C INTERFACE VCC RH0 RH1 RH2 RH3 GND RL0 RL1 RL2 RL3 RW0 RW1 RW2 RW3 SCL SDA A0 A1 A2 WR3 WR2 WR1 WR0 SHDN POWER-UP INTERFACE, CONTROL AND STATUS LOGIC NON- VOLATILE REGISTERS Pin Descriptions TSSOP PIN NUMBER TQFN PIN NUMBER PIN NAME DESCRIPTION 1 3 RH3 “High” terminal of DCP3 2 4 RL3 “Low” terminal of DCP3 3 5 RW3 “Wiper” terminal of DCP3 4 6 A2 Device address input for the I2C interface 5 7 SCL Open drain I2C interface clock input 6 8 SDA Open drain Serial data I/O for the I2C interface 7 9 GND Device ground pin 8 10 RW2 “Wiper” terminal of DCP2 9 11 RL2 “Low” terminal of DCP2 10 12 RH2 “High” terminal of DCP2 11 13 RW1 “Wiper” terminal of DCP1 12 14 RL1 “Low” terminal of DCP1 13 15 RH1 “High” terminal of DCP1 14 16 A0 Device address input for the I2C interface ISL22346 |
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