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GS2962 Scheda tecnica(PDF) 10 Page - Gennum Corporation

Il numero della parte GS2962
Spiegazioni elettronici  Integrated Narrow-Bandwidth PLL
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Produttore elettronici  GENNUM [Gennum Corporation]
Homepage  http://www.gennum.com
Logo GENNUM - Gennum Corporation

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GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
10 of 82
B5, C5, D5,
E2, E5, E6,
F4, F5, F6,
F7, G9, H5,
H6
CORE_GND
Input Power
Reserved. Connect to CORE_GND.
B7
VCO_VDD
Input Power
Power pin for VCO. Connect to 1.2V DC analog followed by an RC
filter (see Typical Application Circuit on page 77). VCO_VDD is
nominally 0.7V.
B8
VCO_GND
Input Power
Ground connection for VCO. Connect to analog GND.
B9, B10
A_GND
Input Power
GND pins for sensitive analog circuitry. Connect to analog GND.
C4V/VSYNCSynch-
ronous
with
PCLK
Input
PARALLEL DATA TIMING.
Signal levels are LVCMOS / LVTTL compatible.
TIM_861 = LOW:
The V signal is used to indicate the portion of the video field/frame
that is used for vertical blanking, when DETECT_TRS is set LOW.
The V signal should be set HIGH for the entire vertical blanking
period and should be set LOW for all lines outside of the vertical
blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The VSYNC signal indicates vertical timing. See Section 4.3 for
timing details.
The VSYNC signal is ignored when DETECT_TRS = HIGH.
C6, C7, C8PLL_GND
Input Power
Ground connection for PLL. Connect to analog GND.
C9, D9, E9,
F9
CD_GND
Input Power
Ground connection for the serial digital cable driver. Connect to
analog GND.
C10, D10
SDO, SDO
Output
Serial Data Output Signal.
Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gbs,
1.485Gb/s, 1.485 /1.001Gb/s or 270Mb/s.
The slew rate of the output is automatically controlled to meet
SMPTE 424M, SMPTE 292 and 259M specifications according to the
setting of the RATE_SEL0 and RATE_SEL1 pins.
D3
STANDBY
Input
Standby input.
HIGH to place the device in Standby mode.
D4
SDO_EN/DIS
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Used to enable or disable the serial digital output stage.
When SDO_EN/DIS is LOW, the serial digital output signals SDO and
SDO are disabled and become high impedance.
When SDO_EN/DIS is HIGH, the serial digital output signals SDO and
SDO are enabled.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description


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