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ISL28023FR60Z Scheda tecnica(PDF) 10 Page - Intersil Corporation |
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ISL28023FR60Z Scheda tecnica(HTML) 10 Page - Intersil Corporation |
10 / 55 page ISL28023 10 FN8389.4 June 17, 2015 Submit Document Feedback CPIN SMBDAT and SMBCLK Pin Capacitance TA = +25°C, f = 1MHz, I2CVCC = 5V, VIN =0V, VOUT = 0V 10 pF fSMBCLK SMBCLK Frequency 400 kHz tIN Pulse Width Suppression Time at SMBDAT and SMBCLK Inputs Any pulse narrower than the max spec is suppressed 50 ns tAA SMBCLK Falling Edge to SMBDAT Output Data Valid SMBCLK falling edge crossing 30% of I2CVCC, until SMBDAT exits the 30% to 70% of I2CVCC window 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SMBDAT crossing 70% of I2CVCC during a STOP condition, to SMBDAT crossing 70% of I2CVCC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of I2CVCC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of I2CVCC crossing 600 ns tSU:STA START Condition Setup Time SMBCLK rising edge to SMBDAT falling edge. Both crossing 70% of I2CVCC 600 ns tHD:STA START Condition Hold Time From SMBDAT falling edge crossing 30% of I2CVCC to SMBCLK falling edge crossing 70% of I2CVCC 600 ns tSU:DAT Input Data Setup Time From SMBDAT exiting the 30% to 70% of VCC window, to SMBCLK rising edge crossing 30% of I2CVCC 100 ns tHD:DAT Input Data Hold Time From SMBCLK falling edge crossing 30% of I2CVCC to SMBDAT entering the 30% to 70% of I2CVCC window 20 900 ns tSU:STO STOP Condition Setup Time From SMBCLK rising edge crossing 70% of I2CVCC, to SMBDAT rising edge crossing 30% of I2CVCC 600 ns tHD:STO STOP Condition Hold Time From SMBDAT rising edge to SMBCLK falling edge. Both crossing 70% of I2CVCC 600 ns tDH Output Data Hold Time From SMBCLK falling edge crossing 30% of I2CVCC, until SMBDAT enters the 30% to 70% of I2CVCC window 0ns tR SMBDAT and SMBCLK Rise Time From 30% to 70% of I2CVCC 20 + 0.1 x Cb 300 ns tF SMBDAT and SMBCLK Fall Time From 70% to 30% of I2CVCC 20 + 0.1 x Cb 300 ns Cb Capacitive Loading of SMBDAT or SMBCLK Total on-chip and off-chip 10 400 pF RPU SMBDAT and SMBCLK Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2kΩ~2.5kΩ For Cb = 40pF, max is about 15kΩ~20kΩ 1kΩ POWER SUPPLY Vvcc Power Supply Voltage at VCC 3.0 3.3 5.5 V Vi2cvcc Power Supply Voltage at I2CVCC f = DC to 400kHz 1.2 3.3 5.5 V Only ADC in Conversion Mode All other blocks are disabled 690 830 µA Electrical Specifications TA=+25°C,I2CVCC=VCC=3.3V,VINP=VBUS=12V,VSENSE=VINP-VINM=80mV,AUXP-AUXM=80mV,AuxV = 3V, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. (Continued) PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 6)TYP MAX (Note 6)UNIT |
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