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SM320C6701-EP Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SM320C6701-EP Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 66 page SMJ320C6701 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SGUS060A − DECEMBER 2007 − REVISED JULY 2009 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Highest Performance Floating-Point Digital Signal Processor (DSP) SMJ320C6701 − 7-, 6-ns Instruction Cycle Time − 140-, 167-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − Up to 1 GFLOPS Performance − Pin-Compatible With ’C6201 Fixed-Point DSP D SMJ: QML Processing to MIL-PRF-38535 D SM: Standard Processing D Operating Temperature Ranges − Extended (W) − 55 °C to 115°C − Extended (S) − 40 °C to 90°C D VelociTI Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core − Eight Highly Independent Functional Units: − Four ALUs (Floating- and Fixed-Point) − Two ALUs (Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Hardware Support for IEEE Single-Precision Instructions − Hardware Support for IEEE Double-Precision Instructions − Byte-Addressable (8-, 16-, 32-Bit Data) − 32-Bit Address Range − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D 1M-Bit On-Chip SRAM − 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) − 512K-Bit Dual-Access Internal Data (64K Bytes) D 32-Bit External Memory Interface (EMIF) − Glueless Interface to Synchronous Memories: SDRAM and SBSRAM − Glueless Interface to Asynchronous Memories: SRAM and EPROM D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D 16-Bit Host-Port Interface (HPI) − Access to Entire Memory Map D Two Multichannel Buffered Serial Ports (McBSPs) − Direct Interface to T1/E1, MVIP, SCSA Framers − ST-Bus-Switching Compatible − Up to 256 Channels Each − AC97-Compatible − Serial-Peripheral-Interface (SPI) Compatible (Motorola ) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked-Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible D 429-Pin Ceramic Ball Grid Array (CBGA) Package (GLP Suffix) and Land Grid Array (CLGA) Package (ZMB Suffix) D 0.18-µm/5-Level Metal Process − CMOS Technology D 3.3-V I/Os, 1.9-V Internal Copyright 2009, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. |
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