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UC1715-SP Scheda tecnica(PDF) 2 Page - Texas Instruments

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Il numero della parte UC1715-SP
Spiegazioni elettronici  COMPLIMENTARY SWITCH FET DRIVERS
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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UC1715-SP Scheda tecnica(HTML) 2 Page - Texas Instruments

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UC1715-SP
SLUSAU8 – MAY 2013
www.ti.com
DEVICE INFORMATION
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
1, 7, 8,
N/C
9, 10,
-
N/C pins are not bonded out. External connections will not affect device functionality.
12, 13
The VCC input range is from 7 V to 20 V. This pin should be bypassed with a capacitor to GND consistent with
VCC
2
I
peak load current demands.
The PWR output waits for the T1 delay after the INPUT’s rising edge before switching on, but switches off
immediately at INPUT’s falling edge (neglecting propagation delays). This output is capable of sourcing 1-A
PWR
3
O
and sinking 2-A of peak gate drive current. PWR output includes a passive, self-biased circuit which holds this
pin active low, when ENBL
≥ 0.8 V regardless of VCC’s voltage.
This is the reference pin for all input voltages and the return point for all device currents. It carries the full
GND
4, 5
-
peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be
damped or clamped such that GND remains the most negative potential.
The AUX switches immediately at INPUT’s rising edge but waits through the T2 delay after INPUT’s falling
AUX
6
edge before switching. AUX is capable of sourcing 0.5-A and sinking 1-A of drive current. During sleep mode,
AUX is inactive with a high impedance.
This pin functions in the same way as T1 but controls the time delay between PWR turn-off and activation of
the AUX switch.
The resistor on this pin sets the charging current on internal timing capacitors to provide independent time
control. The nominal voltage level at this pin is 3 V and the current is internally limited to 1 mA. The total delay
T2
11
from INPUT to output includes a propagation delay in addition to the programmable timer but since the
propagation delays are approximately equal, the relative time delay between the two outputs can be assumed
to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the
Typical Characteristics curves.
The input switches at TTL logic levels (approximately 1.4 V) but the allowable range is from 0 V to 20 V,
allowing direct connection to most common IC PWM controller outputs. The rising edge immediately switches
the AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly, the INPUT
falling edge immediately turns off the PWR output and initiates a timing delay, T2, before switching the AUX
INPUT
14
I
output.
It should be noted that if the input signal comes from a controller with FET drive capability, this signal provides
another option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide the
delay at the trailing edge.
A resistor to ground programs the time delay between AUX switch turn-off and PWR turn-on.
The resistor on this pin sets the charging current on internal timing capacitors to provide independent time
control. The nominal voltage level at this pin is 3 V and the current is internally limited to 1 mA. The total delay
T1
15
from INPUT to output includes a propagation delay in addition to the programmable timer but since the
propagation delays are approximately equal, the relative time delay between the two outputs can be assumed
to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the
Typical Characteristics curves.
The ENBL input switches at TTL logic levels (approximately 1.2 V), and its input range is from 0 V to 20 V.
ENBL
16
I
The ENBL input will place the device into sleep mode when it is a logical low. The current into VCC during the
sleep mode is typically 220
μA.
2
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