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UC1715-SP Scheda tecnica(PDF) 5 Page - Texas Instruments |
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UC1715-SP Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 14 page UC1715-SP www.ti.com SLUSAU8 – MAY 2013 ELECTRICAL CHARACTERISTICS VCC = 15 V, ENBL ≥ 2 V, RT1 = 100 kΩ from T1 to GND, RT2 = 100 kΩ from T2 to GND, TA = TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Overall VCC 7 18 V ICC, nominal ENBL = 3 V 25 mA ICC, sleep mode ENBL = 0.8 V 300 µA Power Driver (PWR) Pre turn-on PWR output, low VCC = 0 V, IOUT = 10 mA, ENBL ≤ 0.8 V 2 V INPUT = 0.8 V, IOUT = 40 mA 1 PWR output low, sat. (VPWR) V INPUT = 0.8 V, IOUT = 100 mA 1.5 INPUT = 3 V, IOUT = −40 mA 3 PWR output high, sat. (VCC − VPWR) V INPUT = 3 V, IOUT = −100 mA 3 Rise time CL = 2200 pF 60 ns Fall time CL = 2200 pF 60 ns T1 delay, AUX to PWR(1) INPUT rising edge, RT1 = 10 kΩ, see (2) 45 200 ns T1 delay, AUX to PWR(1) INPUT rising edge, RT1 = 100 kΩ, see (2) 250 1300 ns PWR prop delay INPUT falling edge, 50%, see (3) 300 ns Auxiliary Driver (AUX) AUX pre turn-on AUX output low (VPAUX) VCC = 0 V, ENBL ≤ 0.8 V, IOUT = 10 mA 2 V VIN = 3 V, IOUT = 40 mA 1 AUX output low, sat. (VAUX) V VIN = 3 V, IOUT = 100 mA 1.5 VIN = 0.8 V, IOUT = -40 mA 3 AUX output high, sat. (VCC – VAUX) V VIN = 0.8 V, IOUT = -100 mA 3 Rise time CL = 2200 pF 60 ns Fall time CL = 2200 pF 60 ns T2 delay, PWR to AUX(1) INPUT falling edge, RT2 = 10 kΩ, see (2) 45 130 ns T2 delay, PWR to AUX(1) INPUT falling edge, RT2 = 100 kΩ, see (2) 200 700 ns AUX prop delay INPUT rising edge, 50%, see (3) 185 ns Enable (ENBL) Input threshold 2.8 V Input current, IIH ENBL = 15 V -10 10 µA Input current, IIL ENBL = 0 V -15 15 µA T1 Current limit T1 = 0 V -2 -0.5 mA Nominal voltage at T1 2.7 3.3 V Minimum T1 delay T1 = 2.5 V, see (2) 80 ns T2 Current limit T2 = 0 V -2 -0.5 mA Nominal voltage at T12 2.7 3.3 V Minimum T2 delay T2 = 2.5 V, see (2) 80 ns Input (INPUT) Input threshold 2.8 V Input current, IIH ENBL = 15 V -10 10 µA Input current, IIL ENBL = 0 V -20 20 µA (1) The parameter is guaranteed to the limit specified by characterization, but not production tested. (2) T1 and T2 delay is defined as the time between the 50% transition point of AUX (PWR) and the 50% transition point of PWR (AUX) with no capacitive load on either output. (3) Propagation delays are measured from the 50% point of the input signal to the 50% point of the output signal’s transition with no load on outputs. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: UC1715-SP |
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