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LMZ21701 Scheda tecnica(PDF) 10 Page - Texas Instruments |
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LMZ21701 Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 37 page LMZ21701 SNVS853D – AUGUST 2012 – REVISED NOVEMBER 2014 www.ti.com 8.4 Feature Description 8.4.1 Input Under Voltage Lockout The LMZ21701 features input under voltage lockout (UVLO) circuit. It monitors the input voltage level and prevents the device from switching the power MOSFETs if VIN is not high enough. The typical VIN UVLO rising threshold is 2.9 V with 180 mV of hysteresis. 8.4.2 Enable Input (EN) The enable pin (EN) is weakly pulled down internally through a 400 k Ω resistor to keep EN logic low when the pin is floating. The pull-down resistor is not connected when EN is set high. Once the voltage on the enable pin (EN) is set high the Nano Module will start operation. If EN is set low ( < 0.3 V ) the LMZ21701 will enter shutdown mode. The typical shutdown quiescent current is 1.5 μA. 8.4.3 Softstart and Tracking Function (SS) When EN is set high for device operation the LMZ21701 will start switching after 50 μs delay and the output voltage will start rising. The VOUT rising slope is controlled by the external capacitor CSS connected to the softstart (SS) pin. The Nano Module has a 2.9 μA constant current source internally connected to the SS pin to program the softstart time TSS: TSS = CSS x 1.25 V / 2.9 μA (1) The softstart capacitor voltage is reset to zero volts when EN is pulled low and when the thermal protection is active. If tracking function is desired, the SS pin can be used to track external voltage. If the applied external tracking voltage is between 100 mV and 1.2 V, the FB voltage will follow SS according to the following relationship: VFB = 0.64 x VSS (2) 8.4.4 Power Good Function (PG) The LMZ21701 features a power good function which can be used for sequencing of multiple rails. The PG pin is an open-drain output and requires a pull-up resistor RPG to VOUT (or any other external voltage less than 7 V). When the Nano Module is enabled and UVLO is satisfied, the power good function starts monitoring the output voltage. The PG pin is kept at logic low if the output has not reached the proper regulation voltage. Refer to the Electrical Characteristics table for the PG voltage thresholds. The PG pin can sink 2 mA of current which sets the minimum limit of the RPG resistance value: RPG-MIN= VPULL-UP / 2 mA (3) The PG pin goes low impedance if the device is disabled or the thermal protection is active. 8.4.5 Output Voltage Setting The output voltage of the LMZ21701 is set by a resistive divider from VOUT to GND, connected to the feedback (FB) pin. The output voltage can be set between 0.9 V and 6 V. The voltage at the FB pin is regulated to 0.8 V. The recommended minimum divider current is 2 μA. This sets a maximum limit on the bottom feedback resistor RFBB. Its value should not exceed 400 kΩ. The top feedback resistor RFBT can be calculated using the following formula: RFBT = RFBB x (VOUT/ 0.8 – 1) (4) 8.4.6 Output Current Limit and Output Short Circuit Protection The LMZ21701 has integrated protection against heavy loads and output short circuit events. Both, the high-side FET and low-side FET have current monitoring circuitry. If the current limit threshold of the high-side FET is reached , the high-side FET will be turned off and the low-side FET will be turned on to ramp down the inductor current. Once the current through the low-side FET has decreased below a safe level, the high-side device will be allowed to turn on again. The actual DC output current depends on the input voltage, output voltage, and switching frequency. Refer to the Application Curves section for more information. 10 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LMZ21701 |
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