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SM3G Scheda tecnica(PDF) 11 Page - Connor-Winfield Corporation |
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SM3G Scheda tecnica(HTML) 11 Page - Connor-Winfield Corporation |
11 / 36 page SM3G5 Data Sheet #: TM083 Page 11 of 36 Rev: 05 Date: 01/26/11 © Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Detailed Description continued Output Signals and Frequency Output 1istheprimaryoutput,andinlockedmodeissynchronizedtotheselectedreference.Output 1mustbespecifiedatthe timeoforderingasanyoneofthefollowingfrequencies:12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz. M/S Output isan8kHzoutputavailableasaframereferenceorsynchronizationsignalforcross-coupledpairsofSM3Gdevices operatedinmaster/slavemode.Inmastermode,M/SOutputissynchronizedtotheselectedreference.Inslavemode,M/SOutput isinphasewiththe M/S REFoffsetbythevaluewrittentothePhase_offset register(+31.75to-32nS,with.25nSresolution).M/S Outputmaybea50%dutycyclesignal,orvariablehigh-goingpulsewidth,asdeterminedbythe Ctl_ModeandFr_Pulse_Width registers.Invariablepulsewidthmode,thewidthmaybefrom1to15multiplesoftheOutput1cycletime.SeeRegisterDescriptions andOperationsection. BITS_ClkistheBITSclockoutputateither1.544MHzor2.048MHz.ItisselectedbytheT1/E1inputanditsstatemaybereadin bit3ofthe Ctl_Moderegister.WhenT1/E1=1,theBITSfrequencyis1.544MHz,andwhenT1/E1=0,theBITSfrequencyis2.048 MHz.ThisoutputclockisdigitallysynthesizedfromOutput1directlyandwillbesynchronizedtoM/SOutput. Interrupts TheSM3Gmodulesupportseightdifferentinterruptsandappearsin INTR_EVENT (0x12)register.Eachinterruptcanbe individuallyenabledordisabledviathe INTR_ENABLE (0x13)register.Eachbitenablesordisablesthecorrespondinginterruptfrom assertingthe SPI_INTpin.InterrupteventsstillappearintheINTR_EVENT (0x12)registerindependentoftheirenablestate.All interruptsareclearedonce INTR_EVENT (0x12)registerisread.Theinterruptsare: • Anyreferencechangingfromavailabletonotavailable • Anyreferencechangingfromnotavailabletoavailable • M/S REFchangingfromactivitytonoactivity • M/S REFchangingfromnoactivitytoactivity • DPLLModestatuschange • Referenceswitchinautomaticreferenceselectionmode • LossofSignal • LossofLock Interrupts and Reference Change in Autonomous Mode Interruptscanbeusedtodeterminethecauseofareferencechangeinautonomousmode.Letusassumethatthemoduleis currentlylockedto REF1.ThemoduleswitchestoREF2andSPI_INTpinisasserted.TheuserreadstheINTR_EVENT (0x12) register. Ifthemoduleisoperatinginautonomousrevertivemode,thecausecanbedeterminedfrombits1,4,5,6and7.Bit5issetto indicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7isset thenthecauseofthereferencechangeisaLossofLockalarmontheactivereference.IfBit1issetthenthecauseofthereference changeistheavailabilityofahigherpriorityreference. Note:TheDPLLModeStatusChangebit(Bit4)isalsosettoindicateachangeinDPLL_STATUS (0x11)register,duringan interruptcausedbyareferencechange.Thedatain DPLL_STATUS (0x11)registerhoweverisnotusefulindeterminingthecauseof areferencechange.Thisisbecausebits0-2ofthisregisteralwaysreflectsthestatusofthecurrentactivereferenceandhencecannot beusedtodeterminethestatusofthelastactivereference. Interrupts in Manual Mode Inmanualoperatingmode,whentheactivereferencefailsduetoaLossofSignalorLossofLockalarm,aninterruptisgenerated. Forexample,incaseofaLossofSignal,bits4and6of INTR_EVENT (0x12) registerwouldbesettoindicateLossofSignaland DPLLModeStatusChange.Theusermaychoosetoreadthe DPLL_STATUS (0x11)register,thoughinmanualmodebit6ofINTR_ EVENT (0x12)registerisamirrorofbit0ofDPLL_STATUS (0x11)register.ThisholdstrueforaLossofLockalarm,wherebit7of INTR_EVENT (0x12) registerisamirrorofbit1ofDPLL_STATUS (0x11)register. Internal Clock Calibration Theinternalclockmaybecalibratedbywritingafrequencyoffsetv.s.nominalfrequencyintotheCalibrationregister.This calibrationisusedbythesynchronizationsoftwaretocreateafrequencycorrectedfromtheactualinternalclockoutputbythevalue writtentotheCalibrationregister.Seeregisterdescriptions. |
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