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9ZXL1231 Scheda tecnica(PDF) 7 Page - Integrated Device Technology

Il numero della parte 9ZXL1231
Spiegazioni elettronici  Space-saving 64 VFQFPN package
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Produttore elettronici  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo IDT - Integrated Device Technology

9ZXL1231 Scheda tecnica(HTML) 7 Page - Integrated Device Technology

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REVISION F 07/14/15
7
DB1200ZL 12-OUTPUT LOW POWER HCSL BUFFER
9ZXL1231 DATASHEET
Electrical Characteristics–Input/Supply/Common Output Parameters
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Supply Voltage
VDDx
Supply voltage, except VDDIO
3.135
3.3
3.465
V
Output Supply Voltage
VDDIO
Supply voltage for DIF outputs, if present
0.95
1.05
3.465
V
Commmercial range (TCOM)0
70
°C
Industrial range (TIND)
-40
85
°C
Input High Voltage
VIH
Single-ended inputs, except SMBus, tri-level
inputs
2VDD + 0.3
V
Input Low Voltage
VIL
Single-ended inputs, except SMBus, tri-level
inputs
GND - 0.3
0.8
V
Input High Voltage
VIHTRI
Tri-Level Inputs
2.2
VDD + 0.3
V
Input Mid Voltage
VIMTRI
Tri-Level Inputs
1.2
VDD/2
1.8
V
Input Low Voltage
VILTRI
Tri-Level Inputs
GND - 0.3
0.8
V
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
5
uA
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
Fibyp
VDD = 3.3 V, Bypass mode
33
150
MHz
Fipll
VDD = 3.3 V, 100MHz PLL mode
90
100.00
110
MHz
Fipll
VDD = 3.3 V, 133.33MHz PLL mode
120
133.33
147
MHz
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs, except DIF_IN
1.5
5
pF
1
CINDIF_IN
DIF_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.18
1.8
ms
1,2
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30
33
kHz
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4
10
clocks
1,2,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
tF
Fall time of control inputs
5
ns
2
Trise
tR
Rise time of control inputs
5
ns
2
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
Capacitance
3Time from deassertion until outputs are >200 mV
4DIF_IN input
Ambient Operating
Temperature
TAMB
Input Current
Input Frequency


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