9ZXL0651

6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI

IDT®

6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI

11

9ZXL0651

REV C 040115

SMBusTable: PLL Mode, and Frequency Select Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

PLL Mode 1

PLL Operating Mode Rd back 1

R

Latch

Bit 6

PLL Mode 0

PLL Operating Mode Rd back 0

R

Latch

Bit 5

0

Bit 4

0

Bit 3

PLL_SW_EN

Enable S/W control of PLL BW

RW

HW Latch

SMBus Control

0

Bit 2

PLL Mode 1

PLL Operating Mode 1

RW

1

Bit 1

PLL Mode 0

PLL Operating Mode 1

RW

1

Bit 0

1

SMBusTable: Output Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

1

Bit 6

DIF_3_En

Output Control - '0' overrides OE# pin

RW

1

Bit 5

DIF_2_En

Output Control - '0' overrides OE# pin

RW

1

Bit 4

1

Bit 3

1

Bit 2

DIF_1_En

Output Control - '0' overrides OE# pin

RW

1

Bit 1

DIF_0_En

Output Control - '0' overrides OE# pin

RW

1

Bit 0

1

SMBusTable: Output Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

1

Bit 2

DIF_5_En

Output Control - '0' overrides OE# pin

RW

1

Bit 1

DIF_4_En

Output Control - '0' overrides OE# pin

RW

1

Bit 0

1

SMBusTable: Reserved Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

SMBusTable: Reserved Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

Reserved

Low/Low

Enable

Low/Low

Enable

Reserved

Reserved

Reserved

Reserved

Reserved

Low/Low

Enable

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Byte 3

Byte 4

Reserved

Reserved

Reserved

Byte 0

2

2

36/37

26/27

23/24

Byte 1

17/18

14/15

Byte 2

See PLL Operating Mode

Readback Table

See PLL Operating Mode

Readback Table

Note: Setting bit 3 to '1' allows the user to overide the Latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating

Mode Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the system will have to

accomplished if the user changes these bits.

33/34

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved