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8V79S674 Scheda tecnica(PDF) 3 Page - Integrated Device Technology |
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8V79S674 Scheda tecnica(HTML) 3 Page - Integrated Device Technology |
3 / 21 page 8V79S674 DATA SHEET REVISION 2 04/10/15 3 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER Truth Tables Table 3A. Nx Clock Divider Function Table Table 3B. nOEA Output Enable Function Table Table 3C. nOEB Output Enable Function Table Input Divider Value N1 N0 0 (default) 0 (default) ÷1 01 ÷2 10 ÷4 11 ÷8 Input Output Operation nOEA 0 (default) Q0 is enabled 1 Q0 is disabled in logic Low state Input Output Operation nOEB 0 (default) Q1, Q2 and Q3 are enabled 1 Q1, Q2 and Q3 are disabled in logic Low state |
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