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8V41N010 Scheda tecnica(PDF) 5 Page - Integrated Device Technology |
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8V41N010 Scheda tecnica(HTML) 5 Page - Integrated Device Technology |
5 / 26 page REVISION 1 06/30/15 5 CLOCK GENERATOR FOR CAVIUM PROCESSORS 8V41N010 DATA SHEET NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Function Tables Table 3A. FSEL_X Control Input Function Table NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E. NOTE: Any two outputs operated at the same frequency will be synchronous. Table 3B. PLL_SEL Control Input Function Table Table 3C. REF_SEL Control Input Function Table Table 3D. OE_[A:E] Control Input Function Table 65 nc Unused No internal connection. 66 FSEL_D1 Input Pulldown Selects the QDx, nQDx output frequency. LVCMOS/LVTTL interface levels. 0 = 100MHz (default) 1 = 156.25MHz 67 VDD Power Core supply. 68 nMR Input Pulldown Active LOW Master Reset. LVCMOS/LVTTL interface levels. 0 = Reset. The internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. (default) 1 = Active. The internal dividers and the outputs are active. 69 VDDO Power Output supply. 70 nc Unused No internal connection. 71 GND Power Power supply ground. 72 nc Unused No internal connection. ePAD GND_EP Power Exposed pad of package. Connect to GND. Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance CLK, nCLK 2.5 pF Control Pins 6 pF RPULLUP Input Pullup Resistor 50 k RPULLDOWN Input Pulldown Resistor 50 k ROUT Output Impedance QF VDDO_QF = 3.465V 15 Table 1. Pin Descriptions Number Name Type Description Input Output Frequency FSEL_X1 Q[Ax:Ex], nQ[Ax:Ex] 0 (default) 100MHz 1156.25MHz Input Operation PLL_SEL 0 PLL Bypass 1 (default) PLL Mode Input Clock Source REF_SEL 0 CLK, nCLK 1 (default) XTAL_IN, XTAL_OUT Input Outputs OE_[A:E] Q[Ax:Ex], nQ[Ax:Ex] 0 High-Impedance 1 (default) Enabled |
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