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74LV165 Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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74LV165 Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 21 page 74LV165 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 6 — 19 February 2014 10 of 21 NXP Semiconductors 74LV165 8-bit parallel-in/serial-out shift register [1] Typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPHL and tPLH. [3] Typical values are measured at VCC = 3.3 V. [4] Typical values are measured at VCC = 5.0 V. [5] CPD is used to determine the dynamic power dissipation PD = CPD VCC2 fi + (CL VCC2 fo) (PD in W), where: fi = input frequency in MHz; fo = output frequency in MHz; (C L VCC 2 f o) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 11. Waveforms fmax maximum frequency see Figure 7 VCC = 2.0 V 14 40 - 12 - MHz VCC = 2.7 V 19 60 - 16 - MHz VCC = 3.0 V to 3.6 V [3] 24 65 - 20 - MHz VCC = 3.3 V; CL = 15 pF - 78 - - - MHz VCC = 4.5 V to 5.5 V [4] 36 75 - 30 - MHz CPD power dissipation capacitance VI =GND to VCC; VCC = 3.3 V [5] -35 - pF Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit, see Figure 12 Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Measurement points are given in Table 8. The changing to output assumes that internal Q6 is opposite state from Q7. Fig 7. Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and maximum clock frequency |
Codice articolo simile - 74LV165_15 |
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Descrizione simile - 74LV165_15 |
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