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74LV165 Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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74LV165 Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
4 / 21 page 74LV165 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 6 — 19 February 2014 4 of 21 NXP Semiconductors 74LV165 8-bit parallel-in/serial-out shift register 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 5. Pin configuration (DIP16, SO16 and (T)SSOP16) Table 2. Pin description Symbol Pin Description PL 1 parallel enable input (active LOW) CP 2 clock input (LOW-to-HIGH edge-triggered) Q7 7 complementary serial output from the last stage GND 8 ground (0 V) Q7 9 serial output from the last stage DS 10 serial data input D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs CE 15 clock enable input (active LOW) VCC 16 positive supply voltage |
Codice articolo simile - 74LV165_15 |
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Descrizione simile - 74LV165_15 |
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