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RDD104 Scheda tecnica(PDF) 2 Page - LSI Computer Systems |
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RDD104 Scheda tecnica(HTML) 2 Page - LSI Computer Systems |
2 / 2 page DYNAMIC ELECTRICAL CHARACTERISTICS: (CL = 50pF, Input Rise and Fall Times = 20ns except for Clock, unless otherwise specified.) VDD MIN MAX UNIT Clock Input Frequency 4.5V 0 1.5 MHz 10V 0 4.0 MHz 15V 0 6.0 MHz Clock Input Rise & Fall Times 4.5 to 15V - No Limit Clock Input Rise & Fall Time, 4.5V - 140 ns CL = 15pF 10V - 70 ns Clock Output Propagation 4.5V - 300 ns Delay, CL = 15pF 10V - 150 ns Output Rise & Fall Times 4.5V - 400 ns 10V - 200 ns Propagation Delay to Output 4.5V - 1500 ns 10V - 750 ns Reset Pulse Width 4.5V 800 - ns 10V 400 - ns Reset Removal Time 4.5V - 500 ns 10V - 250 ns Reset Propagation Delay 4.5V - 1400 ns to Output 10V - 700 ns Select Input Setup Time 4.5V - 800 ns 10V - 400 ns MINIMUM PARTS OSCILLATOR CIRCUIT PIN 6 10M PIN 5 FIGURE 2. TYPICAL OSCILLATOR CIRCUIT WITH TRIM -1 MHZ AND BELOW PIN 5 PIN 6 20M 10M 100pF 40pF FIGURE 3. PIN 5 PIN 6 39pF 10M FIGURE 4. TYPICAL OSCILLATOR CIRCUIT WITH TRIM - ABOVE 1 MHZ 56pF 50pF 20pF CLOCK INPUT SIGNAL R1 V SS V DD V DD 5 FIGURE 5. TYPICAL INPUT If input signals are less than VSS or greater than VDD, a series input resistor, R1, should be used to limit the maximum input current to 2 milliamperes. BUFFER +V -V 1 OUT OF 4 SELECTOR DECODER 8 3 7 5 4 1 2 FIGURE 6. RDD 104 BLOCK DIAGRAM CLOCK GENERATOR ÷ ÷ ÷ ÷ 10 10 10 10 R CLOCK IN CLOCK OUT RESET DIVIDER SELECT-1 DIVIDER SELECT-2 6 OSCILLATOR EXTERNAL COMPONENTS OUTPUT V DD V SS 3 STAGE INVERTING AMPLIFIER RDD104-011000-2 |
Codice articolo simile - RDD104 |
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Descrizione simile - RDD104 |
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