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U18680EJ1V0PM00 Scheda tecnica(PDF) 10 Page - Renesas Technology Corp |
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U18680EJ1V0PM00 Scheda tecnica(HTML) 10 Page - Renesas Technology Corp |
10 / 30 page Preliminary Product Information U18680EJ1V0PM00 8 µPD78F9221CS, 78F9222CS 1.2 Non-port Functions Pin Name I/O Function After Reset Alternate- Function Pin INTP0 P30/TI000 INTP1 P43/TxD6 INTP2 P31/TI010/TO00 INTP3 Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input P41 RxD6 Input Serial data input for asynchronous serial interface Input P44 TxD6 Output Serial data output for asynchronous serial interface Input P43/INTP1 TI000 External count clock input to 16-bit timer/event counter 00. Capture trigger input to capture registers (CR000 and CR010) of 16-bit timer/event counter 00 P30/INTP0 TI010 Input Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 Input P31/TO00/INTP2 TO00 Output 16-bit timer/event counter 00 output Input P31/TI010/INTP2 TOH1 Output 8-bit timer H1 output Input P42 ANI0 to ANI3 Input Analog input of A/D converter Input P20 to P23 AVREF − Reference voltage of A/D converter − − RESET Input System reset input − P34 X1 Input Connection of crystal/ceramic resonator for system clock oscillation. External clock input − P121 X2 − Connection of crystal/ceramic resonator for system clock oscillation. − P122 VDD − Positive power supply − − VSS − Ground potential − − Caution The P121/X1 and P122/X2 pins are pulled down during reset. |
Codice articolo simile - U18680EJ1V0PM00_15 |
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Descrizione simile - U18680EJ1V0PM00_15 |
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