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ADMCF340 Scheda tecnica(PDF) 11 Page - Analog Devices |
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ADMCF340 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 40 page REV. A ADMC(F)340 –11– FLASH MEMORY SUBSYSTEM The ADMC(F)340 has 4K × 24-bit user-programmable, nonvola- tile flash memory. A flash programming utility is provided with the development tools and performs the basic device programming operations: erase, program, and verify. The flash memory array is portioned into three asymmetrically sized sectors of 256 words, 256 words, and 3,584 words, labeled Sector 0, Sector 1, and Sector 2, respectively. These sectors are mapped into external program memory address space. Four flash memory interface registers are connected to the DSP. These 16-bit registers are mapped into the register area of data memory space. They are named Flash Memory Control Register (FMCR), Flash Memory Address Register (FMAR), Flash Memory Data Register Low (FMDRL), and Flash Memory Data Register High (FMDRH). These registers are diagrammed beginning with Figure 21. They are used by the flash memory programming utility. The user program may read these registers but should not modify them directly. The flash programming utility provides a complete interface to the flash memory. Note that from the point of view of 2171 core, the flash memory is placed externally. It means the core accesses them through an external memory interface that multiplexes the program memory and data memory buses into a single external bus. Therefore, if more than one external transfer must be made in the same instruction, there will be at least one overhead cycle required. Special Flash Registers The flash module has four nonvolatile 8-bit registers called Special Flash Registers (SFRs) that are accessible independently of the main flash array via the flash programming utility. These registers are for general-purpose, nonvolatile storage. When erased, the Special Flash Registers contain all 0s. To read Special Flash Registers from the user program, call the read_reg routine contained in the ROM. Refer to the ADMCF34x DSP Motor Controller Developers’ Reference Manual for an example. Boot-from-Flash Code A security feature is available in the form of a code that when set causes the processor to execute the program in flash memory at power-up or reset. In this mode, the flash programming utility and debugger are unable to communicate with the ADMC(F)340. Consequently, the contents of the flash memory can be neither programmed nor read. The boot-from-flash code may be set via the flash programming utility when the user’s program is thoroughly tested and loaded into flash program memory at Address 0x2200. The user’s pro- gram must contain a mechanism for clearing the boot-from-flash code if reprogramming the flash memory is desired. The only way to clear boot-from-flash is from within the user program, by calling the flash_init or auto_erase_reg routines that are included in the ROM. The user program must be signaled in some way to call the necessary routine to clear the boot-from-flash code. An example would be to detect a high level on a PIO pin during startup initialization and then call the flash_init or auto-erase-reg routine. The flash_init routine will erase the entire user program in flash memory before clearing the boot-from-flash code, thus ensuring the security of the user program. If security is not a concern, the auto_erase_reg routine can be used to clear the boot-from-flash code while leaving the user program intact. Refer to the ADMCF34x DSP Motor Controller Developers’ Reference Manual for further instructions and an example of using the boot-from-flash code. FLASH PROGRAM BOOT SEQUENCE On power-up or reset, the processor begins instruction execution at Address 0x0800 of internal program ROM. The ROM monitor program that is located there checks the boot-from-flash code. If that code is set, the processor jumps to location 0x2200 in external flash program memory, where it expects to find the user’s application program. If the boot-from-flash code is not set, the monitor attempts to boot from an external device as described in the ADMCF34x DSP Motor Controller Developers’ Reference Manual. SYSTEM INTERFACE Figure 4 shows a basic system configuration for the ADMC(F)340 with an external crystal. ADMC(F)340 XTAL CLKIN 10MHz CLKOUT RESET 22pF 22pF Figure 4. Basic System Configuration Clock Signals The ADMC(F)340 can be clocked either by a crystal or a TTL compatible clock signal. For normal operation, the CLKIN input cannot be halted, changed during operation, or operated below the specified minimum frequency. If an external clock is used, it should be a TTL compatible signal running at half the instruction rate. The signal is connected to the CLKIN pin of the ADMC(F)340. In this mode, with an external clock signal, the XTAL pin must be left unconnected. The ADMC(F)340 uses an input clock with a frequency equal to half the instruc- tion rate; a 10 MHz input clock yields a 50 ns processor cycle (which is equivalent to 20 MHz). Normally, instructions are executed in a single processor cycle. All device timing is rela- tive to the internal instruction rate that is indicated by the CLKOUT signal when enabled. Because the ADMC(F)340 includes an on-chip oscillator feedback circuit, an external crystal may be used instead of a clock source, as shown in Figure 2. The crystal should be connected across the CLKIN and XTAL pins with two capacitors (see Figure 2). A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output signal (CLKOUT) is generated by the processor at the processor’s cycle rate of twice the input frequency. |
Codice articolo simile - ADMCF340_15 |
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Descrizione simile - ADMCF340_15 |
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