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ADMCF340 Scheda tecnica(PDF) 10 Page - Analog Devices

Il numero della parte ADMCF340
Spiegazioni elettronici  64-Lead Flash and ROM Memory
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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REV. A
ADMC(F)340
–10–
• SPORT0 has one pin, SCLK0, shared with SPORT1.
During a boot phase (SPORT1 Boot Mode enabled by a bit
in the MODECTRL Register), the serial clock of SPORT1 is
externally available. The serial clock of SPORT0 is externally
available when the SPORT1 is configured in UART Mode.
• SPORT0 can be configured as a SPI Port (master mode only).
Refer to Table XI for more information. The clock phase and
polarity are programmable through the MODECTRL Register.
Refer to Table XI for pin configuration.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word or 32-word time division multiplexed
serial bit stream.
• SPORT1 is the default port for program/data memory boot
loading and for the development tools interface. The DT1/FL1
pin can be configured as the SROM/E
2 PROM reset signal.
The ADMC(F)340 is available in a 64-lead LQFP package.
PIN FUNCTION DESCRIPTION
Table I. Pin List
Pin Group
No. of Input/
Name
Pins
Output Function
PWMPOL
1
I
PWM Polarity
PWMSR
1I
PWM Switched
Reluctance Mode
RESET
1I
Processor Reset Input
SPORT1
1
2
I/O
Serial Port 1 Pins
(DT1/FL1, DR1)
SPORT0
1
5
I/O
Serial Port 0 Pins
(DT0, DR0, RFS0,
TFS0, SCLK1/
SCLK0
2)
CLKOUT
1
1
1
I/O
Processor Clock
Output
CLKIN, XTAL
2
I/O
External Clock or
Quartz Crystal
Connection Point
PORTA0–PORTA8
1
9
I/O
Digital I/O Port Pins
PORTB0–PORTB15 16
I/O
Digital I/O Port Pins
AUX0–AUX1
1
2O
Auxiliary PWM
Outputs
AH-CL
6
O
PWM Outputs
PWMTRIP
1I
PWM Trip Signal
V1 to V3
3
I
ISENSE Inputs
ISENSE1 to ISENSE3
3I
Analog Inputs
VAUX0-VAUX7
7
I
Auxiliary Analog Inputs
ICONST
1
O
ADC Constant
Current Source
DVDD
3I
Power Supply
AVDD
3I
Power Supply
GND
3
I
Ground
NOTES
1Multiplexed pins, individually selectable through PORTA_SELECT and
PORTA_DATA Registers.
2SCLK1/SCLK0 multiplexed signals, selectable through MODECTRL
Register Bit 4.
INTERRUPT OVERVIEW
The ADMC(F)340 can respond to 34 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 27 of which are from the motor control peripherals.
The seven DSP core interrupts are SPORT1 receive (or
IRQ0)
and transmit (or
IRQ1), SPORT0 receive and transmit, the
internal timer, and two software interrupts. The motor control
peripheral interrupts are the 25 programmable I/Os and two from
the PWM (PWMSYNC pulse and
PWMTRIP). All motor control
interrupts are multiplexed into the DSP core through the periph-
eral
IRQ2 interrupt. The interrupts are internally prioritized and
individually maskable. A detailed description of the entire interrupt
system of the ADMC(F)340 is presented in the Interrupt
Control section, which follows the detailed descriptions of each
peripheral block.
MEMORY MAP
The ADMC(F)340 has two distinct memory types: program
and data. In general, program memory contains user code and
coefficients, while the data memory is used to store variables and
data during program execution. Three kinds of program memory are
provided on the ADMC(F)340: RAM, ROM, and FLASH. The
motor control peripherals are memory mapped into a region of the
data memory space starting at 0x2000. The complete program and
data memory maps are given in Tables II and III, respectively.
Table II. Program Memory Map
Memory
Address Range
Type
Function
0x0000–0x002F
RAM
Internal Vector Table
0x0030–0x01FF
RAM
User Program Memory
0x0200–0x07FF
Reserved
0x0800–0x17FF
ROM
Reserved Program Memory
0x1800–0x1FFF
Reserved
0x2000–0x20FF
FLASH
User Program Memory
Sector 0
0x2100–0x21FF
FLASH
User Program Memory
Sector 1
0x2200–0x2FFF
FLASH
User Program Memory
Sector 2
0x3000–0x3FFF
Reserved
Table III. Data Memory Map
Memory
Address Range
Type
Function
0x0000–0x1FFF
Reserved
0x2000–0x20FF
Memory Mapped Registers
0x2100–0x37FF
Reserved
0x3800–0x39FF
RAM
User Data Memory
0x3A00–0x3BFF
RAM
Reserved
0x3C00–0x3FFF
Memory Mapped Registers


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