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ADF7025 Scheda tecnica(PDF) 11 Page - Analog Devices

Il numero della parte ADF7025
Spiegazioni elettronici  High Performance ISM Band Transceiver IC
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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ADF7025 Scheda tecnica(HTML) 11 Page - Analog Devices

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Data Sheet
ADF7025
Rev. B | Page 11 of 44
Pin No.
Mnemonic
Description
29
GND2
Ground for Digital Section.
30
ADCIN
Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin.
Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin.
31
VREG2
Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed
between this pin and ground for regulator stability and noise rejection.
32
VDD2
Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible
to this pin.
33
INT/LOCK
Bidirectional Pin. In output mode (interrupt mode), the ADF7025 asserts the INT/LOCK pin when
it has found a match for the preamble sequence.
In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold
when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received.
In this mode, a demodulator lock can be asserted with minimum delay.
34
DATA I/O
Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply.
35
DATA CLK
In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the
center of the received data.
36
CLKOUT
A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used
to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
37
MUXOUT
This pin provides the lock_detect signal, which is used to determine if the PLL is locked to the correct
frequency. Other signals include regulator_ready, which is an indicator of the status of the serial interface
regulator.
38
OSC2
The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.
39
OSC1
The reference crystal should be connected between this pin and OSC2.
40
VDD3
Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground
with a 0.01 µF capacitor.
41
VREG3
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor
should be placed between this pin and ground for regulator stability and noise rejection.
42
CPOUT
Charge Pump Output. This output generates current pulses that are integrated in the loop filter.
The integrated current changes the control voltage on the input to the VCO.
43
VDD
Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor.
44 to 47
GND
Grounds for VCO Block.
48
CVCO
A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.
EPAD
Exposed Pad. Connect the exposed pad to GND.


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