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AD9886 Scheda tecnica(PDF) 1 Page - Analog Devices |
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AD9886 Scheda tecnica(HTML) 1 Page - Analog Devices |
1 / 32 page REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9886 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Analog Interface for Flat Panel Displays FUNCTIONAL BLOCK DIAGRAM CLAMP RIN A/D 8 8 8 ROUTA ROUTB CLAMP GIN A/D 8 8 8 GOUTA GOUTB CLAMP BIN A/D 8 8 8 BOUTA BOUTB SYNC PROCESSING AND CLOCK GENERATION HSYNC COAST CLAMP CKINV CKEXT FILT 2 DATACK HSOUT VSOUT SOGOUT ANALOG INTERFACE REF REFOUT REFIN SERIAL REGISTER AND POWER MANAGEMENT SCL SDA A1 A0 AD9886 FEATURES Analog Interface 140 MSPS Maximum Conversion Rate 330 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 140 MSPS 3.3 V Power Supply Full Sync Processing Midscale Clamp for YUV Applications GENERAL DESCRIPTION The AD9886 is a complete 8-bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports resolutions up to SXGA (1280 × 1024 at 75 Hz). For ease of design and to minimize cost, the AD9886 is a fully integrated interface solution for FPDs. The AD9886 includes a 140 MHz triple ADC with internal 1.25 V reference, PLL to generate a pixel clock from an HSYNC, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and an HSYNC signal. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9886’s on-chip PLL generates a pixel clock from an HSYNC. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC and Clock output phase relationships are maintained. The PLL can be disabled and an external clock input provided as the pixel clock. The AD9886 also offers full sync processing for composite sync and sync-on- green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully pro- grammable via a 2-wire serial interface. |
Codice articolo simile - AD9886_15 |
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Descrizione simile - AD9886_15 |
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