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Specifications CD40174BMS

Logic Diagram

FIGURE 1. 1 OF 6 FLIP-FLOPS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION

OPEN

GROUND

VDD

9V

± -0.5V

OSCILLATOR

50kHz

25kHz

Static Burn-In 1

(Note 1)

2, 5, 7, 10, 12, 15 1, 3, 4, 6, 8, 9, 11,

13, 14

16

Static Burn-In 2

(Note 1)

2, 5, 7, 10, 12, 15

8

1, 3, 4, 6, 9, 11,

13, 14, 16

Dynamic Burn-In

(Note 1)

-

8

1, 16

2, 5, 7, 10, 12, 15

9

3, 4, 6, 11, 13, 14

Irradiation

(Note 2)

2, 5, 7, 10, 12, 15

8

1, 3, 4, 6, 9, 11,

13, 14, 16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K

± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K

± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V

± 0.5V

TRUTH TABLE FOR 1 OF 6 FLIP-FLOPS

INPUTS

OUTPUT

CLOCK

DATA

CLEAR

Q

010

111

X1

NC

XX

0

0

1 = High Level

2 = Low Level

X = Don’t Care

NC = No Change

VDD

VSS

p

n

p

n

p

n

p

n

CL

D

CL

CL

CL

CL

CL

CL

3 (4, 6, 11, 13, 14)

CL

Q

CLR*

1

2 (5, 7, 10, 12, 15)

CL

CL

CLK*

9

* All inputs (terms 1, 3, 4, 6, 9, 11, 13, 14)

protected by COS/MOS protection network