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CA3310AD Scheda tecnica(PDF) 4 Page - Intersil Corporation

Il numero della parte CA3310AD
Spiegazioni elettronici  CMOS, 10-Bit, A/D Converters with Internal Track and Hold
Download  15 Pages
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA3310AD Scheda tecnica(HTML) 4 Page - Intersil Corporation

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6-9
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage VDD. . . . . . . . . . . . . . .VSS -0.5V to VSS +7V
Analog Supply Voltage (VAA+) . . . . . . . . . . . . . . . . . . . . . VDD ±0.5V
Any Other Terminal . . . . . . . . . . . . . . . . .VSS -0.5V to VDD + 0.5V
DC Input Current or Output (Protection Diode)
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20mA
DC Output Drain Current, per Output . . . . . . . . . . . . . . . . . .
±35mA
Total DC Supply or Ground Current . . . . . . . . . . . . . . . . . . .
±70mA
Operating Conditions
Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Package Type E, M . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . .
75
N/A
SBDIP Package . . . . . . . . . . . . . . . . . . . .
70
22
SOIC Package . . . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature (TSTG) . . . . . . . . . .-65
oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25
oC, V
DD = VAA+ = 5V, VREF+ = 4.608V, VSS = VAA- = VREF- = GND, CLK = External 1MHz,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY (See Text For Definitions)
Resolution
10
-
-
Bits
Differential Linearity Error
CA3310
-
±0.5
±0.75
LSB
CA3310A
-
±0.25
±0.5
LSB
Integral Linearity Error
CA3310
-
±0.5
±0.75
LSB
CA3310A
-
±0.25
±0.5
LSB
Gain Error
CA3310
-
±0.25
±0.5
LSB
CA3310A
-
-
±0.25
LSB
Offset Error
CA3310
-
±0.25
±0.5
LSB
CA3310A
-
-
±0.25
LSB
ANALOG OUTPUT
Input Resistance
In Series with Input Sample
Capacitors
-
330
-
Input Capacitance
During Sample State
-
300
-
pF
Input Capacitance
During Hold State
-
20
-
pF
Input Current
At VIN = VREF+ = 5V
-
-
+300
µA
At VIN = VREF - = 0V
-
-
-100
µA
Static Input Current
STRT = V+, CLK = V+
At VIN = VREF+ = 5V
--
1
µA
At VIN = VREF - = 0V
-
-
-1
µA
Input + Full-Scale Range
(Note 2)
VREF- +1
-
VDD +0.3
V
Input - Full-Scale Range
(Note 2)
VSS -0.3
-
VREF+ -1
V
Input Bandwidth
From Input RC Time Constant
-
1.5
-
MHz
DIGITAL INPUTS DRST, OEL, OEM, STRT, CLK
High-Level Input Voltage
Over VDD = 3V to 6V (Note 2)
70
-
-
% of
VDD
Low-Level Input Voltage
Over VDD = 3V to 6V (Note 2)
-
-
30
% of
VDD
Input Leakage Current
Except CLK
-
-
±1
µA
Input Capacitance
(Note 2)
-
-
10
pF
Input Current
CLK Only (Note 2)
-
-
±400
µA
CA3310, CA3310A


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