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CA3310A Scheda tecnica(PDF) 5 Page - Intersil Corporation |
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CA3310A Scheda tecnica(HTML) 5 Page - Intersil Corporation |
5 / 15 page 6-10 DIGITAL OUTPUTS D0 - D9, DRDY High-Level Output Voltage ISOURCE = -4mA 4.6 - - V Low-Level Output Voltage ISINK = 6mA - - 0.4 V Three-State Leakage Except DRDY - - ±1 µA Output Capacitance Except DRDY (Note 2) - - 20 pF CLK OUTPUT High-Level Output Voltage ISOURCE = 100µA (Note 2) 4 - - V Low-Level Output Voltage ISlNK = 100µA (Note 2) - - 1 V TIMING Clock Frequency Internal, CLK and REXT Open 200 300 400 kHz Internal, CLK Shorted to REXT 600 800 1000 kHz External, Applied to CLK (Note 2) (Max) - 4 2 MHz (Min) 100 10 - kHz Clock Pulse Width, tLOW, tHIGH External, Applied to CLK: See Figure 1 (Note 2) 100 - - ns Conversion Time Internal, CLK Shorted to REXT 13 - - µs Aperture Delay, tD APR See Figure 1 - 100 - ns Clock to Data Ready Delay, tD1 DRDY See Figure 1 - 150 - ns Clock to Data Ready Delay, tD2 DRDY See Figure 1 - 250 - ns Clock to Data Delay, tD Data See Figure 1 - 200 - ns Start Removal Time, tR STRT See Figures 3 and 4 (Note 1) - -120 - ns Start Setup Time, tSU STRT See Figure 4 - 160 - ns Start Pulse Width, tW STRT See Figures 3 and 4 - 10 - ns Start to Data Ready Delay, tD3 DRDY See Figures 3 and 4 - 170 - ns Clock Delay from Start, tD CLK See Figure 3 - 200 - ns Ready Reset Removal Time, tR DRST See Figure 50 (Note 1) - -80 - ns Ready Reset Pulse Width, tW DRST See Figure 5 - 10 - ns Ready Reset to Data Ready Delay, tD4 DRDY See Figure 5 - 35 - ns Output Enable Delay, tEN See Figure 2 - 40 - ns Output Disable Delay, tDIS See Figure 2 - 50 - ns SUPPLIES Supply Operating Range, VDD or VAA (Note 2) 3 - 6 V Supply Current, IDD + IAA See Figures 14, 15 - 3 8 mA Supply Standby Current Clock Stopped During Cycle 1 - 3.5 - mA Analog Supply Rejection At 120Hz, See Figure 13 - 25 - mV/V Reference Input Current See Figure 10 - 160 - µA TEMPERATURE DEPENDENCY Offset Drift At 0 to 1 Code Transition - -4 - µV/oC Gain Drift At 1022 to 1023 Code Transition - -6 - µV/oC Internal Clock Speed See Figure 7 - -0.5 - %/oC NOTES: 1. A (-) removal time means the signal can be removed after the reference signal. 2. Parameter not tested, but guaranteed by design or characterization. Electrical Specifications TA = 25 oC, V DD = VAA+ = 5V, VREF+ = 4.608V, VSS = VAA- = VREF- = GND, CLK = External 1MHz, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CA3310, CA3310A |
Codice articolo simile - CA3310A |
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Descrizione simile - CA3310A |
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