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AD5384 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD5384 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 33 page Data Sheet AD5384 TIMING CHARACTERISTICS Serial Interface DVDDx = 2.7 V to 5.5 V; AVDDx = 4.5 V to 5.5 V; AGNDx = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. The AD5384 must remain powered up when part of a multidevice system with a common I2C bus. Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDDx) and are timed from a voltage level of 1.2 V. See Figure 2, Figure 3, Figure 4, and Figure 5. Table 3. Parameter Min Typ Max Unit Description t1 33 ns SCLK cycle time t2 13 ns SCLK high time t3 13 ns SCLK low time t4 13 ns SYNC falling edge to SCLK falling edge setup time t51 13 ns 24th SCLK falling edge to SYNC falling edge t61 33 ns Minimum SYNC low time t7 10 ns Minimum SYNC high time t7A 140 ns Minimum SYNC high time in readback mode t8 5 ns Data setup time t9 4.5 ns Data hold time t101 36 ns 24th SCLK falling edge to BUSY falling edge t11 670 ns BUSY pulse width low (single channel update) t121 20 ns 24th SCLK falling edge to LDAC falling edge t13 20 ns LDAC pulse width low t14 100 2000 ns BUSY rising edge to DAC output response time t15 0 ns BUSY rising edge to LDAC falling edge t16 100 ns LDAC falling edge to DAC output response time t17 3 µs DAC output settling time boost mode off t18 20 ns CLR pulse width low t19 40 µs CLR pulse activation time t202 30 ns SCLK rising edge to SDO valid t212 5 ns SCLK falling edge to SYNC rising edge t222 8 ns SYNC rising edge to SCLK rising edge t23 20 ns SYNC rising edge to LDAC falling edge 1 Standalone mode only. 2 Daisy-chain mode only. CL 50pF TO OUTPUT PIN VOH (MIN) OR VOL (MAX) 200µA 200µA IOL IOH Figure 2. Load Circuit for Digital Output Timing Rev. C | Page 7 of 33 |
Codice articolo simile - AD5384_15 |
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Descrizione simile - AD5384_15 |
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