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MC146805E2 Scheda tecnica(PDF) 7 Page - InnovASIC, Inc |
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MC146805E2 Scheda tecnica(HTML) 7 Page - InnovASIC, Inc |
7 / 31 page IA6805E2 Data Sheet Microprocessor Unit As of Production Version 00 Copyright © 2002 ENG21108140100 www.innovasic.com innovASIC Customer Support: The End of Obsolescence ™ Page 7 of 31 1-888-824-4184 Registers: The following paragraphs describe the registers contained in the MPU. Figure 6 shows the programming model and Figure 7 shows the interrupt stacking order. NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER 1 1 1 I N T E R R U P T DECREASING MEMORY ADDRESSES STACK PCH 0 0 0 PCL R E T U R N INCREASING MEMORY ADDRESSES UNSTACK A X SP 1 0 0 0 0 0 0 H I N Z C 7 0 CC CONDITION CODE REGISTER CARRY/BORROW HALF CARRY INTERRUPT MASK NEGATIVE ZERO STACK POINTER PROGRAM COUNTER INDEX REGISTER ACCUMULATOR 7 0 12 0 7 8 PCH PCL 12 6 0 4 0 Figure 6. Programming Model Figure 7. Interrupt Stacking Order |
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