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AD394 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD394 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 12 page AD394 Rev. A | Page 7 of 12 THEORY OF OPERATION The AD394 quad DAC provides four-quadrant multiplication. It is a hybrid IC comprised of four, monolithic, 12-bit, CMOS, multiplying DACs and eight precision output amplifiers. Each of the four independent-buffered channels has an independent reference input capable of accepting a separate dc or ac signal for multiplying or for function generation applications. The CMOS DACs act as digitally programmable attenuators when used with a varying input signal or, if used with a fixed dc reference, the DAC would act as a standard bipolar output DAC. In addition, each DAC has a 12-bit wide data latch to buffer the converter when connected to a microprocessor data bus. MULTIPLYING MODE Figure 5 shows the transfer function. The diagram indicates an area over which many different combinations of the reference input and digital input can result in a particular analog output voltage. The highlighted transfer line in the diagram indicates the transfer function if a fixed reference is at the input. The digital code above the diagram indicates the midpoint and endpoints of each function. The relationship between the reference input (VREFIN), the digital input code, and the analog output is given in Table 4. Note that the reference input signal sets the slope of the transfer function (and determines the full- scale output at code 111...111), while the digital input selects the horizontal position in each diagram. Figure 5. The AD394 as a Four-Quadrant Multiplier of Reference and Digital Input DATA AND CONTROL SIGNAL FORMAT The AD394 accepts 12-bit parallel data in response to Control Signals CS1–CS4. As detailed in Table 3, the four chip select lines are used to address the DAC register of interest. It is per- missible to have more than one chip select active at any time. If CS1–CS4 are all brought low coincident, all four DAC outputs will be updated to the value located on the data bus. All control inputs are level-triggered and may be hard-wired low to render any register (or group of registers) transparent. Table 3. DAC Select Matrix CS1 CS2 CS3 CS4 Operation 1 1 1 1 All DACs latched 0 1 1 1 Load DAC 1 from data bus 1 0 1 1 Load DAC 2 from data bus 1 1 0 1 Load DAC 3 from data bus 1 1 1 0 Load DAC 4 from data bus 0 0 0 0 All DACs simultaneously loaded Table 4. Bipolar Code Table Data Input Analog Output Analog Output Voltage, VREFIN = 10 V 1111 1111 1111 1 × (VREFIN) ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ 2048 2047 9.9951 V Full Scale − 1 LSB 1100 0000 0000 1 × (VREFIN) ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ 2048 1024 5.000 V 1/2 Scale 1000 0000 0001 1 × (VREFIN) ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ 2048 1 4.88 mV 1 LSB 1000 0000 0000 1 × (VREFIN) ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ 2048 0 0.000 V Zero 0111 1111 1111 −1 × (VREFIN) ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ 2048 1 −4.88 mV −1LSB 0100 0000 0000 −1 × (VREFIN) ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ 2048 1024 −5.000 V −1/2 Scale 0000 0000 0000 −1 × (VREFIN) ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ 2048 2048 −10.000 V −Full Scale |
Codice articolo simile - AD394_15 |
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Descrizione simile - AD394_15 |
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