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TP0604N3-G Scheda tecnica(PDF) 1 Page - Supertex, Inc

Il numero della parte TP0604N3-G
Spiegazioni elettronici  P-Channel Enhancement-Mode Vertical DMOS FET
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Produttore elettronici  SUTEX [Supertex, Inc]
Homepage  http://www.supertex.com
Logo SUTEX - Supertex, Inc

TP0604N3-G Scheda tecnica(HTML) 1 Page - Supertex, Inc

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Supertex inc.
Supertex inc.
www.supertex.com
TP0604
Doc.# DSFP-TP0604
C082012
Features
Low threshold (-2.4V max.)
High input impedance
Low input capacitance (95pF typical)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
P-Channel Enhancement-Mode
Vertical DMOS FET
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
BV
DSS
Drain-to-gate voltage
BV
DGS
Gate-to-source voltage
±20V
Operating and storage temperature
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Pin Configuration
TO-92 (N3)
GATE
SOURCE
DRAIN
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiTP
0604
YYWW
TO-92 (N3)
Product Marking
Package may or may not include the following marks: Si or
Ordering Information
Part Number
Package Option
Packing
TP0604N3-G
3-Lead TO-92
1000/Bag
TP0604N3-G P002
3-Lead TO-92
2000/Reel
TP0604N3-G P003
TP0604N3-G P005
TP0604N3-G P013
TP0604N3-G P014
TP2404NW
Die in wafer form
---
TP2404NJ
Die on adhesive tape ---
TP2404ND
Die in waffle pack
---
Product Summary
BV
DSS/BVDGS
(V)
R
DS(ON)
(max) (Ω)
I
D(ON)
(min) (A)
V
GS(th)
(max) (V)
-40
2.0
-2.0
-2.4
For packaged products, -G indicates package is RoHS compliant (‘Green’).
TO-92 taping specifications and winding styles per EIA-468 Standard.
Devices in Wafer / Die form are RoHS compliant (‘Green’).
Refer to Die Specification VF57 for layout and dimensions.


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