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MC-458CB64PSB Scheda tecnica(PDF) 11 Page - NEC |
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MC-458CB64PSB Scheda tecnica(HTML) 11 Page - NEC |
11 / 6 page Data Sheet M12263EJAV0DS00 11 MC-458CB64ESB, 458CB64PSB (2/2) Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 31 Module bank density 10H 0 0 0 1 0 0 0 0 64 M bytes 32 Command and address signal setup time -A10B 25H 0 0 1 0 0 1 0 1 2.5 ns 33 Command and address signal hold time -A10B 10H 0 0 0 1 0 0 0 0 1 ns 34 Data signal input setup time -A10B 25H 0 0 1 0 0 1 0 1 2.5 ns 35 Data signal input hold time -A10B 10H 0 0 0 1 0 0 0 0 1 ns 36-61 00H 0 0 0 0 0 0 0 0 62 SPD revision -A10B 12H 0 0 0 1 0 0 1 0 1.2 63 Checksum for bytes 0 – 62 B5H 1 0 1 1 0 1 0 1 64-71 Manufacture’s JEDEC ID code 72 Manufacturing location 73-90 Manufacture’s P/N 91-92 Revision code 93-94 Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific 126 Intel specification frequency -A10B 66H 0 1 1 0 0 1 1 0 66 MHz 127 Intel specification /CAS latency support -A10B 06H 00 00 01 10 Timing Chart Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E). |
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