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LM3205 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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LM3205 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 24 page 1 2 3 4 5 10 9 8 7 6 LM3205 Top View PGND PGND SGND VCON FB SW PVin PVin VDD EN 1 2 3 4 5 10 9 8 7 6 LM3205 Bottom View PGND PGND SGND VCON FB SW PVin PVin VDD EN Package Marking Top View A1 B1 C1 A3 B3 C3 SW A2 C2 EN PGND SGND VDD FB VCON PVIN A3 B3 C3 A1 B1 C1 A2 C2 VCON SW PGND SGND FB PVIN VDD EN PIN 1 IDENTIFIER Top View Bottom View Package Mark õ Top View LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com CONNECTION DIAGRAMS Figure 2. 8–Bump Thin Micro SMD Package, Large Bump NS Package Number TLA08GNA Figure 3. 10–Pin LLP NS Package Number SDA10A Table 1. PIN DESCRIPTIONS Pin # Name Description microSMD LLP A1 8, 9 PVIN Power Supply Voltage Input to the internal PFET switch. B1 7 VDD Analog Supply Input. C1 6 EN Enable Input. Set this digital input high for normal operation. For shutdown, set low. C2 4 VCON Voltage Control Analog input. VCON controls VOUT in PWM mode. C3 5 FB Feedback Analog Input. Connect to the output at the output filter capacitor. B3 3 SGND Analog and Control Ground A3 1, 2 PGND Power Ground A2 10 SW Switch node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the LM3205. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 |
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