FB

PGOOD

COMP

NC

PVIN

PVIN

SW

SS/TRK

AVIN

VCC

EN

PGND

PGND

SW

AGND

RT

Exposed Pad

On Bottom

(EP)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LM20144

SNVS529F – OCTOBER 2007 – REVISED NOVEMBER 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Connection Diagram

Top View

See Package Number PWP0016A

Pin Descriptions

Pin #

Name

Description

Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor to set the

1

SS/TRK

Soft-Start ramp rate. If driven by a external source less than 800 mV, this pin overrides the internal reference

that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated.

Feedback input to the error amplifier from the regulated output. This pin is connected to the inverting input of

2

FB

the internal transconductance error amplifier. An 800 mV reference connected to the non-inverting input of the

error amplifier sets the closed loop regulation voltage at the FB pin.

Power good output signal. Open drain output indicating the output voltage is regulating within tolerance. A

3

PGOOD

pull-up resistor of 10 k

Ω to 100 kΩ is recommend for most applications.

4

COMP

External compensation pin. Connect a resistor and capacitor to this pin to compensate the device.

This pin has no internal connection. While this pin may be left open, it is strongly recommended that this pin

5

NC

be connected to Ground.

Input voltage to the power switches inside the device. These pins should be connected together at the device.

6,7

PVIN

A low ESR capacitor should be placed near these pins to stabilize the input voltage.

8,9

SW

Switch pin. The PWM output of the internal power switches.

10,11

PGND

Power ground pin for the internal power switches.

Precision enable input for the device. An external voltage divider can be used to set the device turn-on

12

EN

threshold. If not used the EN pin should be connected to PVIN.

13

VCC

Internal 2.7V sub-regulator. This pin should be bypassed with a 1 µF ceramic capacitor.

14

AVIN

Analog input supply that generates the internal bias. Must be connected to VIN through a low pass RC filter.

15

AGND

Quiet analog ground for the internal bias circuitry.

16

RT

Frequency adjust pin. Connecting a resistor on this pin to ground will set the oscillator frequency.

Exposed metal pad on the underside of the package with a weak electrical connection to ground. It is

EP

Exposed Pad

recommended to connect this pad to the PC board ground plane in order to improve heat dissipation and

reduce the package

2

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