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FIN1218 Scheda tecnica(PDF) 3 Page - Fairchild Semiconductor |
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FIN1218 Scheda tecnica(HTML) 3 Page - Fairchild Semiconductor |
3 / 20 page © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 3 Transmitters Pin Configuration Figure 3. FIN1217 / FIN1215 (21:3 Transmitter) Pin Definitions Pin Names I/O Type # of Pins Description of Signals TxIn I 21 LVTTL Level Inputs TxCKLIn I 1 LVTTL Level Clock Input; the rising edge is for data strobe TxOut+ O 3 Positive LVDS Differential Data Output TxOut O 3 Negative LVDS Differential Data Output TxCLKOut+ O 1 Positive LVDS Differential Clock Output TxCLKOut- O 1 Negative LVDS Differential Clock Output /PwrDn I 1 LVTTL Level Power-Down Input; assertion (LOW) puts the outputs in high- impedance state PLL VCC I 1 Power Supply Pin for LVDS Outputs PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pins for LVDS Outputs LVDS GND I 3 Ground Pin for LVDS Outputs VCC I 4 Power Supply Pins for LVTTL Inputs GND I 5 Ground Pins for LVTTL Inputs NC No Connect |
Codice articolo simile - FIN1218 |
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Descrizione simile - FIN1218 |
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