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MC7457RX1267LC Scheda tecnica(PDF) 10 Page - Freescale Semiconductor, Inc |
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MC7457RX1267LC Scheda tecnica(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 71 page  MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441 Freescale Semiconductor 10 Minimum misprediction penalty 6 6 6 Execution Unit Timings (Latency-Throughput) Aligned load (integer, float, vector) 3-1, 4-1, 3-1 3-1, 4-1, 3-1 3-1, 4-1, 3-1 Misaligned load (integer, float, vector) 4-2, 5-2, 4-2 4-2, 5-2, 4-2 4-2, 5-2, 4-2 L1 miss, L2 hit latency 9 data/13 instruction 9 data/13 instruction 9 data/13 instruction SFX (aDd Sub, Shift, Rot, Cmp, logicals) 1-1 1-1 1-1 Integer multiply (32 × 8, 32 × 16, 32 × 32) 3-1, 3-1, 4-2 3-1, 3-1, 4-2 3-1, 3-1, 4-2 Scalar float 5-1 5-1 5-1 VSFX (vector simple) 1-1 1-1 1-1 VCFX (vector complex) 4-1 4-1 4-1 VFPU (vector float) 4-1 4-1 4-1 VPER (vector permute) 2-1 2-1 2-1 MMUs TLBs (instruction and data) 128-entry, 2-way 128-entry, 2-way 128-entry, 2-way Tablewalk mechanism Hardware + software Hardware + software Hardware + software Instruction BATs/data BATs 8/8 8/8 4/4 L1 I Cache/D Cache Features Size 32K/32K 32K/32K 32K/32K Associativity 8-way 8-way 8-way Locking granularity Way Way Way Parity on I cache Word Word Word Parity on D cache Byte Byte Byte Number of D cache misses (load/store) 5/1 5/1 5/1 Data stream touch engines 4 streams 4 streams 4 streams On-Chip Cache Features Cache level L2L2L2 Size/associativity 512-Kbyte/8-way 256-Kbyte/8-way 256-Kbyte/8-way Access width 256 bits 256 bits 256 bits Number of 32-byte sectors/line 2 2 2 Parity Byte Byte Byte Off-Chip Cache Support 1 Table 1. Microarchitecture Comparison (continued) Microarchitectural Specs MPC7457/MPC7447 MPC7455/MPC7445 MPC7450/MPC7451/ MPC7441 |
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