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FIN1049 Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FIN1049 Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 12 page © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN1049 • Rev. 1.0.3 2 Pin Configuration Functional Diagram Figure 1. Pin Configuration Figure 2. Functional Diagram Pin Definitions Pin # Name Description 2, 3 RIN1+, RIN2+ Non-Inverting LVDS Inputs 1, 4 RIN1-, RIN2- Inverting LVDS Inputs 7, 6 DOUT1+, DOUT2+ Non-Inverting Driver Outputs 8, 5 DOUT1-, DOUT2- Inverting Driver Outputs 16, 9 EN, ENb Driver Enable Pins for All Outputs 15, 14 ROUT1, ROUT2 LVTTL Output Pins for ROUT1 and ROUT2 10, 11 DIN1, DIN2 LVTTL Input Pins for DIN1 and DIN2 12 VCC Power Supply (3.3 V) 13 GND Ground Function Table Inputs Outputs (LVTTL) Inputs (LVDS) (1) Outputs (LVDS) EN ENb ROUT1 ROUT2 RINn+ RINn- DOUTn+ DOUTn- H L ON ON ON ON H H Z Z Z Z L H Z Z Z Z L L Z Z Z Z H L H H Open Current Fail-Safe Condition Legend: H=HIGH Logic Level L=LOW Logic Level or OPEN X=Don't Care Z=High Impedance Note: 1. Any unused receiver Inputs should be left open. |
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